totem pole output for ttl logic families

In any case, where there is a grounded (“low”) input, the output is guaranteed to be floating (“high”). The following series of illustrations shows this for three input states (00, 01, and 10): Namely, if either of the inputs is grounded, transistor Q 2 will be forced into a condition of cutoff, thus turning Q 3 off and floating the output (output goes “high”). Since this circuit bears so much resemblance to the simple inverter circuit, the only difference being a second input terminal connected in the same way to the base of transistor Q 2, we can say that each of the inputs will have the same effect on the output. Thus, a 1 in resulted in a 0 out, and vice versa. In the case of the open-collector output configuration, this “high” state was simply “floating.” Allowing the input to float (or be connected to V cc) resulted in the output becoming grounded, which is the “low” or 0 state. In the single-input (inverter) circuit, grounding the input resulted in an output that assumed the “high” (1) state.

This transistor has one collector, one base, and two emitters, and in the circuit, it looks like this: Unfortunately, a simple NPN transistor structure is inadequate to simulate the three PN junctions necessary in this diode network, so a different transistor (and symbol) is needed. Just as in the case of the inverter and buffer, the “steering” diode cluster marked “Q 1” is actually formed like a transistor, even though it isn’t used in any amplifying capacity.

This schematic illustrates a real circuit, but it isn’t called a “two-input inverter.” Through analysis, we will discover what this Circuit’s logic function is and correspondingly what it should be designated as. Suppose we altered our basic open-collector inverter circuit, adding a second input terminal just like the first:

Totem pole output for ttl logic families